Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 10, 2004, Pages 1081-1093

  Heydari, Payam ^a   Mohanavelu, Ravindran ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Broad band circuits; Current mode logic; Device mismatch; Enviromental noise; Tapered buffers; Ultrahigh speed cMOS circuits

Indexed keywords

BANDWIDTH; BUFFER CIRCUITS; ELECTRIC POTENTIAL; EMITTER COUPLED LOGIC CIRCUITS; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LOGIC DESIGN; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

BRAOD-BAND CIRCUITS; CURRENT MODE LOGIC; DEVICE MISMATCH; ENVIRONMENTAL NOISE; TAPERED BUFFERS; ULTRAHIGH-SPEED CMOS CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 6344252617     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.833663     Document Type: Conference Paper

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