Noise in phase-locked loops

2001 Southwest Symposium on Mixed-Signal Design, SSMSD 2001

Volumn , Issue , 2001, Pages 1-6

  Hajimiri, A ^a  

^a California Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOCKS (FASTENERS); PHASE LOCKED LOOPS; PHASE NOISE;

BUILDING BLOCKES; IN-PHASE; PHASE LOCKED LOOP (PLL); PHASE NOISE PERFORMANCE; PHASE-NOISE PROPERTIES;

JITTER;

EID: 84963831325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2001.914927     Document Type: Conference Paper

References (49)

1. H. de Bellescize, "La Reception Synchrone," L'Onde Electrique, vol. 11, pp. 230-240, June 1932.
2. R. Adler, "A Study of Locking Phenomena in Oscillators," Proc. IRE, vol. 34, pp. 351-357, June 1946.
3. L. DeVito, J. Newton, R. Croughwell, J. Bulzacchelli and F. Benkley, "A 52MHz and 155MHz Clock-Recovery PLL," ISSCC Dig. Tech. Papers, pp. 142-3, Feb. 1991.
4. J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, "A Wide-Bandwidth Low-Voltage PLL for PowerPC™ Microprocessors," IEEE J. Solid-State Circuits, vol. 30, no.4, pp. 383-91, April 1995.
5. B. Razavi, K. F. Lee and R. H. Yan, "Design of High-Speed low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 101-9, Feb. 1995.
6. F. M. Gardner, Phaselock Techniques, 2nd Edition, John Wiley & Sons, New York, 1979.
7. U. L. Rohde, J. C. Whitaker and T. T. N. Bucher, Communications Receiver: Principles and Design, 2nd Edition, McGraw-Hill, 1997.
8. W. F. Egan, Frequency Synthesis by Phase Lock, John Wiley and Sons 1981.
9. J, A. Crawford, Frequency Synthesizer Design Handbook, Artech House, Inc. 1994.
10. B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design, IEEE Press, 1996.
11. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, 1998.
12. J. Noordanus, "Frequency Synthesizers - A Survey of Techniques," IEEE Trans. on Comm., vol. COM-18, pp. 632-7, Oct. 1970.
13. J. Tierney, C. M. Rader, B. Gold, "A Digital Frequency Synthesizer," IEEE Trans. on Audio and Electroacoustics, vol. AU-19, no.1, p. 48-57, March 1971.
14. V. F. Kroupa, Frequency Synthesis, Wiley, New York, 1973.
15. G. Gorski-Popiel (Editor), Frequency Synthesis: Applications and Techniques, IEEE Press, New York, 1975.
16. Manassewitsch, Frequency Synthesizers, Wiley, New York, 1976.
17. W. F. Egan, "The Effect of Small Contaminating Signals in Nonlinear Elements Used in Frequency Synthesis and Conversion," Proc. IEEE, vol. 69, no. 7, pp. 797-811, July 1981.
18. V. F. Kroupa, "Noise Properties of PLL Systems," IEEE Trans. Comm., vol. COM-30, no. 10, pp. 2244-52, Oct. 1982.
19. J. Groszkowski, "Frequency Division," Proc. IRE, vol. 18, no. 11, pp. 1960-70, Nov. 1930.
20. H. Sterky, "Frequency Multiplication and Division," Proc. IRE, vol. 25, no. 9, pp. 1153-73, Sept. 1937.
21. R. L. Miller, "Fractional-Frequency Generators Utilizing Regenerative Modulation," Proc. IRE, vol. 27, no. 7, pp. 446-57, July 1939.
22. D. Huffman, "Extremely Low Noise Frequency Dividers," Microwave J., pp. 209-10, Nov. 1985.
23. T. Ohira, T. Hiraoka and H. Kato, "MMIC 14-GHz VCO and Miller Frequency Divider for Low-Noise Local Oscillators," IEEE Trans. Microwave Theory Techniques, vol. MTT-35, no. 7, pp. 657-62, July 1987.
24. M. M. Driscoll, "Phase Noise Performance of Analog Frequency Dividers," IEEE Trans. Ultrasonic, Ferroelectrics and Freq. Cont., vol. 37, no. 4, pp. 295-304, July 1990.
25. J. Groslambert, M. Olivier and E. Rubiola, "High Spectral Purity Frequency Sources Using Low Noise Regenerative Frequency Dividers," Proc. 45th Annual Symposium on Freq. Cont., pp. 636-9, May 1991.
26. E. Rubiola, M. Olivier and J. Groslambert, "Phase Noise in the Regenerative Frequency Dividers," IEEE Tans. Instrumentation and Meas., vol. 41, no. 3, June 1992.
27. G. R. Sloan, "The Modeling, Analysis, and Design of Filter-Based Parametric Frequency Dividers," IEEE Trans. on MTT, vol. 41, no. 2, pp. 224-8, Feb. 1993.
28. O. Llopis, H. Amine, M. Gayral, J. Graffeuil and J. F. Sautereau, "Analytical Model of Noise in an Analog Frequency Divider," IEEE MTT Int. Microwave Symp. Dig., pp. 1033-6, 1993.
29. H. Amine, O. Llopis, R. Plana, J Graffeuil and J.F. Sautereau, "Conversion Gain and Noise in Microwave Analog Frequency Dividers Using Various Types of FET," Proc. 23rd European Microwave Conf., pp. 774-6, Sept. 1993.
30. H. Brauns and W. Konrath, "Ultra Low Phase Noise Parametric Frequency Divider for Highest Performance Microwave- and Millimeter-Wave Frequency Sources," Proc. 25th European Microwave Conf., pp. 1155-8, Sept. 1995.
31. B. Branger, E. LaPorte, J.C. Nallatamby, M. Prigent and L. LaPierre, "Comparison between Simulations and Measurements of Large Signal and Nonlinear Noise Behaviors of MMIC Analog Frequency Divider by Two," IEEE Microwave and Guided Wave Letters, vol. 7, no. 5, May 1997.
32. X. Zhang, X. Zhou and A. S. Daryoush, "A Theoretical and Experimental Study of the Noise Behavior of Subharmonically Injection Locked Local Oscillators," IEEE Trans. on MTT, vol. 40, no. 5, pp. 895-902, May 1992.
33. H. Rategh and T. H. Lee, "Superhamonic Injection Locked Oscillators as Low Power Frequency Dividers," Symp. on VLSI Circ. Dig., pp. 132-5, June 1998.
34. H. Wu and A. Hajimiri, "A 19GHz, 0.5mW, 0.35mm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement," Proc. IEEE ISSCC, Feb. 2001.
35. A. A. L'vovich, "Design of Noise-Immune Counter-Type Frequency Dividers," Elektrosvyaz, Translated in: Telecomm. and Radio Eng., part 1, vol. 29, no. 2, pp. 52-5, Feb. 1975.
36. D. E. Phillips, "Random Noise in Digital Gates and Dividers," Proc. 41st Annual Freq. Cont. Symp., pp. 507-11, 1987.
37. W. F. Egan, "Modeling Phase Noise in Frequency Dividers," IEEE Trans. on Ultrasonic, Ferroelectrics and Freq. Cont., vol. 37, no. 4, pp. 307-15, July 1990.
38. M. R. McClure, "Residual Phase Noise of Digital Frequency Dividers," Microwave J., pp. 124-30, March 1992.
39. B. Miller and R. J. Conley, "A Multiple Modulator Fractional Divider," IEEE Trans. on Instrumentation and Measurement, vol. 40, no. 3, pp. 578-83, June, 1991.
40. Y. Kado, M. Suzuki, K. Koike, Y. Omura and K. Izumi, "A 1-GHz/ 0.9-mW CMOS/SIMOX Divide-by-128/129 Dual-Modulus Prescaler Using a Divide-by-2/3 Synchronous Counter," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 513-17, April 1993.
41. P. Larsson, "High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 744-8, May 1996.
42. B. Chang, J. Park and W. Kim, "A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 749-52, May 1996.
43. J. Craninckx and M. Steyaert, "A 1.75-GHz/3-V Dual Modulus Divide-by-128/129 Prescaler in 0.7-μm CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 890-7, July 1996.
44. A. Hajimiri and T. H. Lee, "A General Theory of Phase Noise in Electrical Oscillators," IEEE J. Solid-State Circuits, vol. 33, no. 2, Feb. 1998.
45. J. Craninckx and M. Steyaert, "Low-noise voltage controlled oscillators using enhanced LC-tanks," IEEE Trans. Circ. Syst.-II, vol. 42, pp. 794-904, Dec. 1995.
46. T. C. Weigandt, B. Kim, and P. R. Gray, "Analysis of Timing Jitter in CMOS Ring Oscillators," Proc. ISCAS, June 1994.
47. J. McNeill, "Jitter in Ring Oscillators," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 870-879, June 1997.
48. D. Ham and A. Hajimiri, "Concepts and Methods in Optimization of Integrated LC VCOs," IEEE J. Solid-State Circuits, vol. 36, no. 6, June 2001.
49. A. Hajimiri, S. Limotyrakis and T. H. Lee, "Phase Noise in Multi-Gigahertz CMOS Ring Oscillators," Proc. Custom Integrated Circuits Conference, May 1998.