Design and analysis of low-voltage current-mode logic buffers

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 293-298

  Heydari, Payam ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bandwidth; Circuits; Delay; Inverters; Logic design; Signal analysis; Signal design; Subthreshold current; Transconductance; Voltage

Indexed keywords

BANDWIDTH; CHAINS; DELAY CIRCUITS; DESIGN; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; NETWORKS (CIRCUITS); SIGNAL ANALYSIS; TRANSCONDUCTANCE;

DELAY; DESIGN AND ANALYSIS; DESIGN PROCEDURE; DIFFERENTIAL ARCHITECTURE; ENVIRONMENTAL NOISE; LOW-VOLTAGE APPLICATIONS; SIGNAL DESIGN; SUB-THRESHOLD CURRENT;

LOGIC CIRCUITS;

EID: 33847159194     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194748     Document Type: Conference Paper

References (7)

1. J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 1996.
2. B. Razavi, "Prospects of CMOS Technology for High-Speed Optical Communication Circuits," IEEE J. Solid-State Circuits, vol. 37, No. 9, pp. 1135-1145, Sept. 2002.
3. M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, "A GHz MOS adaptive pipeline technique using MOS current-mode logic," IEEE J. Solid-State Circuits, vol. 31, No. 6, pp. 784-791, June 1996.
4. M. H. Anis, M. I. Elmasry, "Self-timed MOS current mode logic for digital applications," IEEE Int'l Symp. on Circuits and Systems, vol. 5, pp. 113-116, May 2002.
5. B. Razavi, Design of Analog CMOS Integrated Circuits, pp. 101-134, McGraw-Hill, 2001.
6. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
7. N. Hedenstierna, K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization," IEEE Trans. Computer-Aided Design, vol. CAD-6, No. 2, pp. 270-281, March 1987.