Noise analysis of phase-locked loops

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 277-282

  Mehrotra, Amit ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; COMPUTER AIDED DESIGN; DIFFERENTIAL EQUATIONS; ELECTRIC CHARGE; LOCKS (FASTENERS); NONLINEAR ANALYSIS; NONLINEAR FEEDBACK; OSCILLISTORS; PHASE LOCKED LOOPS; SIGNAL DETECTION; SPECTRUM ANALYSIS; STOCHASTIC SYSTEMS; VARIABLE FREQUENCY OSCILLATORS; WHITE NOISE; COMPUTATIONAL METHODS; COMPUTER SIMULATION; FEEDBACK; NONLINEAR SYSTEMS; TRANSFER FUNCTIONS;

MEASURED RESULTS; OPEN-LOOP VOLTAGE; PHASE DETECTORS; PHASE FREQUENCY DETECTORS; PHASE NOISE ANALYSIS; PHASELOCKED LOOP (PLLS); STOCHASTIC DIFFERENTIAL EQUATIONS; TRANSIENT SIMULATION;

PHASE NOISE; PHASE LOCKED LOOPS;

LOOP FILTER TRANSFER FUNCTION; OPEN LOOP VOLTAGE CONTROLLED OSCILLATOR; PHASE FREQUENCY DETECTOR; PHASE NOISE ANALYSIS; STOCHASTIC DIFFERENTIAL EQUATION;

EID: 0034481269     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896486     Document Type: Conference Paper

References (25)

1. A. Mehrotra, Simulation and Modelling Techniques for Noise in Radio Frequency Integrated Circuits. PhD thesis, University of California, Berkeley, 1999.
2. A. Demir, A. Mehrotra, and J. Roychowdhury, "Phase noise in oscillators: A unifying theory and numerical methods for characterisation, " in Proceedings 1998 Design Automation Conference, pp. 26-31, 1998.
3. V. F. Kroupa and L. Sojdr, "Phase-lock loops of higher orders, " in Second International Conference on Frequency Control and Synthesis, pp. 65-68, 1989.
4. B. Kim, T. C. Weigandt, and P. R. Gray, "PLL/DLL system noise analysis for low jitter clock synthesizer design, " vol. 4, pp. 31-34, 1994.
5. U. L. Rohde, Microwave and wireless synthesizers: Theory and design. Wiley, 1997.
6. J. C. Nallatamby, M. Prigent, J. C. Sarkissian, R. Quere, and J. Obregon, "A new approach to nonlinear analysis of noise behavior of synchronized oscillators and analog-frequency dividers, " IEEE Transactions on Microwave Theory and Techniques, vol. 46, pp. 1168- 1171, Aug. 1998.
7. L. Lin, L. Tee, and P. R. Gray, "A 1.4GHz differential low-noise CMOS frequency syn-thesizer using a wideband PLL architecture, " in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 204-205, 2000.
8. K. Lim, S. Choi, and B. Kim, "Optimal loop bandwidth design for low noise PLL appli-cations, " in Proceedings of the ASP-DAC '97. Asia and South Pacific Design Automation Conference 1997, pp. 425-428, 1997.
9. K. Lim, C.-H. Park, and B. Kim, "Low noise clock synthesizer design using optimal bandwidth, " in Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 163-166, 1998.
10. G. Kolumban, "Frequency domain analysis of sampling phase-locked loops, " in Proceedings 1988 IEEE International Symposium on Circuits and Systems, vol. 1, pp. 611-614, 1988.
11. D. Asta and D. N. Green, "Analysis of a hybrid analog/switched-capacitor phase-locked loop, " IEEE Transactions on Circuits and Systems, vol. 37, pp. 183-197, Feb. 1990.
12. A. Demir, Analysis and simulation of noise in nonlinear electronic circuits and systems. PhD thesis, UC Berkeley, 1997.
13. W. E. Thain Jr. and J. A. Connelly, "Simulating phase noise in phase-locked loops with a circuit simulator, " vol. 3, pp. 1760-1763, 1995.
14. L. Wu, H. Jin, and W. C. Black Jr., "Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems, " in Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, pp. 447-450, 2000.
15. P. Heydani and M. Pedram, "Analysis of jitter due to power-supply noise in phase-locked loops, " in Proceedings of the IEEE2000 Custom Integrated Circuits Conference, pp. 443-446, 2000.
16. B. K. Oksendal, Stochastic differential equations: An introduction with applications. Springer-Verlag, 1998.
17. C. W. Gardiner, Handbook of stochastic methods for physics, chemistry, and the natural sciences, vol. 13 of Springer series in synergetics. Berlin, Heidelberg, New York, Tokyo: Springer-Verlag, seconded., 1983.
18. P. Dupuis and H. J. Kushner, "Stochastic systems with small noise, analysis and simu-lation; a phase locked loop example, " SIAM Journal on Applied Mathematics, vol. 47, pp. 643-661, June 1987.
19. A. Dembo and O. Zeitouni, Large deviations techniques and applications. Boston: Jones and Bartlett, 1993.
20. M. I. Freidlin and A. D. Wentzell, Random Perturbations of Dynamical Systems. Springer-Verlag, 1984.
21. B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw Hill, 2000.
22. J. F. Parker and D. Ray, "A 1, 6-GHz CMOS PLL with on-chip loop filter, " IEEE Journal of Solid-State Circuits, vol. 33, pp. 337-343, Mar. 1998.
23. A. Ali and J. L. Tham, "A 900MHz frequency symthesizer with integrated LC voltage- controlled oscillator, " in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 390-391, 1996.
24. J. Craninckx and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthe-sizer, " in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 372-373, 1998.
25. A. Demir, E. Liu, and A. Sangiovanni-Vincentelli, 'Time-domain non Monte-Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations, " IEEE Transactions for Computer-Aided Design, vol. 15, pp. 493-505, May 1996.