Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 353-360

  Tomita, Yoshihiro ^a   Morifuji, Tadahiro ^a   Ando, Tatsuya ^a   Tago, Masamoto ^a   Kajiwara, Ryoichi ^a   Nemoto, Yoshihiko ^a   Fujii, Tomonori ^a   Kitayama, Yoshifumi ^a   Takahashi, Kenji ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; ENCAPSULATION; INSPECTION; LSI CIRCUITS; NONDESTRUCTIVE EXAMINATION; REACTIVE ION ETCHING; RELIABILITY; SCANNING ELECTRON MICROSCOPY;

LAYERED MICROTHIN ENCAPSULATION; MICRO INTERCONNECTIONS; THREE DIMENTIONAL STACKING TECHNOLOGIES;

ELECTRONICS PACKAGING;

EID: 0034822219     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2001.927748     Document Type: Article

References (11)

1. High-accuracy interconnection technologies on 3D stacking process
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3. Soldability assessment via sequential electrochemical reduction analysis
4. Aging studies of Cu-Sn intermetallic compounds in annealed surface mount solder joints
5. Copper bump bonding with electroless metal cap on 3 dimensional stacked structure
6. Development of encapsulation for the plural narrow gaps of the three-dimensional stacked LSI
7. Three dimensional stacked module structure
8. Underfill flow evaluation using acoustic microscopy