Ultra-high-density 3D chip stacking technology

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1084-1089

  Tanida, Kazumasa ^a   Umemoto, Mitsuo ^a   Tomita, Yoshihiro ^a   Tago, Masamoto ^a   Nemoto, Yoshihiko ^a   Ando, Tatsuya ^a   Takahashi, Kenji ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIES; ELECTRODES; ENCAPSULATION; INTEGRATED CIRCUIT TESTING; SCHEMATIC DIAGRAMS; SILICON WAFERS; THREE DIMENSIONAL;

CHIP STACKING; COPPER BUMP BONDING; NON-CONDUCTIVE PARTICLE PASTE; TEMPERATURE CYCLING TEST;

ELECTRONICS PACKAGING;

EID: 0037592200     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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