Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 238-245

  Sunohara, Masahiro ^a   Fujii, Tomonori ^a   Hoshino, Masataka ^a   Yonemura, Hitoshi ^a   Tomisaka, Manabu ^a   Takahashi, Kenji ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC INSULATION; ELECTRODES; MICROPROCESSOR CHIPS;

WAFER BACKSIDE PROCESSES; WAFER THINNING;

LSI CIRCUITS;

EID: 0036283275     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2002.1008100     Document Type: Article

References (9)

1. Future system-on-silicon lsi chips
2. Current status of research and development for 3D chip stack technology
3. Micro bump interconnections and encapsulation technologies on 3d stacked LSI
4. Additive dependence study on electroplating cu filling for through electrode in silicon wafer of three dimensional LSI chip stacking
5. Electroplating Cu filling study for through electrode in silicon wafer of three dimensional LSI chip stacking
6. Influence on lifetime by backside cu contamination
7. Technologies of wafer thinning and backside insulating for the three-dimensional stacked LSI