Electroplating Cu fillings for through-vias for three-dimensional chip stacking

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1432-1438

  Tomisaka, Manabu ^a   Yonemura, Hitoshi ^a   Hoshino, Masataka ^a   Takahashi, Kenji ^a   Okamura, Takuji ^b   Sun, Jian Jun ^b   Kondo, Kazuo ^b  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

^b OKAYAMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

THREE-DIMENSIONAL CHIP STACKING;

COPPER; ELECTROPLATING; LSI CIRCUITS; MICROPROCESSOR CHIPS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PRINTED CIRCUIT BOARDS; REACTIVE ION ETCHING;

ELECTRONICS PACKAGING;

EID: 0036287852     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2002.1008294     Document Type: Article

References (18)