Bias polarity dependent effects of P+ floating gate EEPROMs

IEEE Transactions on Electron Devices

Volumn 51, Issue 2, 2004, Pages 282-285

  Kuo, Charles ^a   King, Tsu Jae ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Flash memories; Nonvolatile semiconductor memories; Scaling

Indexed keywords

AMORPHOUS SILICON; CHEMICAL VAPOR DEPOSITION; ELECTRIC CURRENT MEASUREMENT; FLASH MEMORY; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; NONVOLATILE STORAGE; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR STORAGE; SILICON WAFERS;

ARSENIC IMPLANTATION; EEPROM; FLOATING GATE; LOW PRESURE CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING SILICON GERMANIDE;

PROM;

EID: 0442295646     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.821702     Document Type: Article

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