Extending gate dielectric scaling limit by NO oxynitride: Design and process issues for sub-100 nm technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 227-230

  Fujiwara, M ^a   Takayanagi, M ^a   Shimizu, T ^a   Toyoshima, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CURRENT VOLTAGE CHARACTERISTICS; DIFFUSION; ELECTRON TUNNELING; FABRICATION; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; NICKEL COMPOUNDS; SEMICONDUCTOR DOPING; THERMAL EFFECTS;

TUNNELING CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 0034453421     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iedm.2000.904298     Document Type: Conference Paper

References (4)