Impact of interconnect architecture on chip size and die yield

Proceedings of the IEEE 1999 International Interconnect Technology Conference, IITC 1999

Volumn , Issue , 1999, Pages 21-23

  Liu, Ruichen ^a   Pai, Chien Shing ^a   Cong, Hong Ih ^a   Lai, Wanen ^a   Martinez, Emilio ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; DIELECTRIC MATERIALS; DIES; LOW-K DIELECTRIC;

DIE SIZE; HIGH-PERFORMANCE LOGIC; INTERCONNECT ARCHITECTURES; ON CHIPS; RC DELAY; TECHNOLOGY NODES; VOLUME PRODUCTION;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 0242621965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1999.787066     Document Type: Conference Paper

References (4)

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2. J. A. Davis, V. K. De and J. D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration - Part I: Derivation and Validation", IEEE Trans. Electron Dev., Vol. 45, p. 580 (1998).
3. P. D. Fisher and R. Nesbitt, "Clock-Cycle Estimation and Test Challenges for Future Microprocessors", IEEE Circuits & Devices, March 1998, p. 37 (1998).
4. th International Conference on Solid-State and Integrated Circuit Technology, Beijing, China, Oct. 1998, pp. 17-20.