Embedding infrastructure IP for SOC yield improvement

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 709-712

  Zorian, Yervant ^a  

^a Virage Logic   (United States)

Author keywords

Embedded Test Repair; Semiconductor IP; Test Resource Partitioning; Yield Optimization

Indexed keywords

EMBEDDED SYSTEMS; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; OPTIMIZATION; SEMICONDUCTOR DEVICE TESTING;

SYSTEM-ON-CHIP (SOC) DESIGNS; TEST RESOURCE PLANNING;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036044639     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2002.1012716     Document Type: Conference Paper

References (6)

1. A strategy for mixed signal yield improvement
2. Embedded robustness IP
3. IP for embedded diagnosis
4. Embedd timing analysis
5. What is infrastructure IP?