Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA)

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 264-273

  Rowlette, Jeremy A ^a   Eiles, Travis M ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

FLIP CHIP DEVICES; FREQUENCIES; LASER BEAM EFFECTS; TIMING CIRCUITS; TRANSISTORS;

LASER ASSISTED DEVICE ALTERATION (LADA);

MICROPROCESSOR CHIPS;

EID: 0142153724     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. D. Josephson, S. Poehlman, V. Govan. "Debug Methodology for the McKinley Processor" Proc. IEEE International. Test Conference, 2001, pp. 451-460.
2. T. Eiles, K. Wilsher, W. Lo, G. Xiao. "Optical Interferometric Probing of Advanced Microprocessors". Proc. IEEE Int. Test Conf., 2000, pp. 80-84.
3. M. Paniccia, T. Eiles, V. Rao, W. Yee. "Novel Optical Probing Technique for Flip Chip Packaged Microprocessors" Proc. IEEE Int. Test Conf., 1998, pp. 740-747.
4. E. Varner, C. Young, H. Ng, S. Maher, T. Eiles, B. Lee. "Single Element Time Resolved Emission Probing for Practical Microprocessor Diagnostic Applications". Proc. 28th International Symposium for Testing & Failure Analysis, 2002, pp. 451-460.
5. J. Tsang, J. Kash, D. Vallett. "Picosecond Imaging Circuit Analysis" IBM J. Res. Develop., 44(4), 2000 p.583-603.
6. R. Livengood, P. Winer, V. Rao. "Application of Advanced Micromachining Techniques for the Characterization and Debug of High Performance Microprocessors". J. Vac. Sci. Tech. B, 17 (1), 1999, pp. 40-43.
7. R. Quo and S. Venkataraman. "A Technique for Fault Diagnosis of Defects in Scan Chains". Proc. IEEE Int. Test Conf., 2001, pp. 268-275.
8. K. Cheng "Partial Scan Designs Without Using a Separate Scan Clock". IEEE 1995, pp. 277-280.
9. S. Rusu and S. Tam. "Clock Generation and Distribution for the First IA-64 Microprocessor". IEEE Int. Sol. State Circuits. Conf., 2000, pp. 176-177.
10. S. Tam, S. Rusu, U. Nagarji Desai, R. Kim, Ji Zhang, I. Young. "Clock Generation and Distribution for the First IA-64 Microprocessor". IEEE J. Sol. State Circuits (35), 2000, pp. 1545-1552.
11. M. Bruce, V. Bruce, D. Eppes, J. Wilcox, E. Cole, P. Tangyunyong, C. Hawkins, "Soft Defect Localization (SDL) on ICs". Proc.28th International Symposium for Testing & Failure Analysis, 2002, pp. 21-27.
12. E. Cole. P. Tangyunyong, C. Hawkins, M. Bruce, V. Bruce, R. Ring, W. Chong. "Resistive Interconnect Localization" Proc.27th International Symposium for Testing & Failure Analysis, 2001, pp. 43-50.
13. M. Pronobis and D. Burns. Proc. International. Symposium for Testing & Failure Analysis, 1982, pp. 178-181.
14. D. Burns, M. Pronobis, C. Eldering, R. Hillman. "Reliability/Design Assessment by Internal-Node Timing-Margin Analysis Using Laser Photocurrent-Injection". Proc. IEEE Int. Reliability Physics Symposium, 1984 pp. 76-82.
15. H. K. Brown, G. C. Fuller, M. S. Clamme. "Timing Margin Examination Using Laser Probing Technique". IEEE 1990, pp. 384-388.
16. Y. Taur and T. Ning. Fundamentals of Modern VLSI Devices. Cambridge University Press1998. pp. 129-130.
17. E. Cole, P. Tangyunyong, D. Barton. "Backside Localization of Open and Shorted Interconnections". Proc. IEEE Int. Reliability Physics Symposium. 1998 pp. 129-136.
18. S. Kolachina, B. Taylor, K. Wills, E. Cole. "Application of TIVA in Design Debug". Proc. 26th International. Symposium for Testing & Failure Analysis, 2000, pp. 497-501
19. 2 SRAM Cell". IEEE Int. Electron. Device Meet. 2002, pp. 61-64.
20. T. Eiles and P. Pardy "Liquid Immersion Objective for High-Resolution Optical Probing of Advanced Microprocessors". Proc. 27th International. Symposium for Testing & Failure Analysis, 2001, pp. 167.