Clock generation and distribution for the first IA-64 microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 176-177

  Rusu, S ^a   Tam, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; LOW PASS FILTERS; MULTIPLYING CIRCUITS; PHASE LOCKED LOOPS; PHASE MEASUREMENT; PULSE GENERATORS;

DUTY CYCLE; REGIONAL CLOCK DRIVERS (RCD);

MICROPROCESSOR CHIPS;

EID: 0034428396     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A 0.35μm CMOS 3-880MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors
2. An adaptive digital deskewing circuit for clock distribution networks
3. A 600 MHz IA-32 microprocessor with enhanced data streaming for graphics and video