A technique for fault diagnosis of defects in scan chains

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 268-277

  Guo, Ruifeng ^a   Venkataraman, Srikanth ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; SHIFT REGISTERS;

FAULT DIAGNOSIS;

VLSI CIRCUITS;

EID: 0035687670     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966642     Document Type: Article

References (9)

1. Partner SRLs for improved shift register diagnostics
2. Diagnosis of scan path failures
3. An efficient scheme to diagnose scan chains
4. Diagnosis of scan chain failures
5. On diagnosis of faults in a scan-chain
6. A method for isolating defects in scannable sequential elements
7. High accuracy flush and scan software diagnostic
8. Scan chain diagnosis using iddq current measurement
9. Poirot: Applications of a logic fault diagnosis tool