ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness

IEEE Transactions on Electron Devices

Volumn 50, Issue 10, 2003, Pages 2126-2134

  Ker, Ming Dou ^a   Hsu, Hsin Chyh ^a   Peng, Jeng Jie ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Electrostatic discharge (ESD); ESD implantation; ESD protection; Machine model

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE MEASUREMENT; ELECTRIC CURRENT MEASUREMENT; ELECTRIC DISCHARGES; SEMICONDUCTOR DEVICE MODELS; VOLTAGE MEASUREMENT;

ELECTROSTATIC DISCHARGE IMPLANTATION; ELECTROSTATIC DISCHARGE PROTECTION; ELECTROSTATIC DISCHARGE ROBUSTNESS;

ELECTROSTATIC DEVICES;

EID: 0141974955     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.817273     Document Type: Article

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