Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors

IEEE Transactions on Electron Devices

Volumn 49, Issue 12, 2002, Pages 2183-2192

  Oh, Kwang Hoon ^a   Duvvury, Charyaka ^b   Banerjee, Kaustav ^c   Dutton, Robert W ^a  

^a Stanford University   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c University of California   (United States)

Author keywords

Ballast resistance; CMOS technology; Electrostatic discharge; Gate to contact spacing; n p n transistor; NMOS transistor; Silicides; Substrate bias; Thermal capacity

Indexed keywords

BALLASTS (LAMP); CMOS INTEGRATED CIRCUITS; DIFFUSION; ELECTRIC CONTACTS; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC RESISTANCE; ELECTROSTATICS; HETEROJUNCTION BIPOLAR TRANSISTORS; SEMICONDUCTING SILICON COMPOUNDS; SPECIFIC HEAT; SUBSTRATES;

ELECTROSTATIC DISCHARGE; GATE-TO-CONTACT SPACING; SALICIDED DEEP SUBMICRON NMOS TRANSISTORS; SILICIDES; SUBSTRATE BIAS;

MOSFET DEVICES;

EID: 0036999719     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.803627     Document Type: Article

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