Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn 2002-January, Issue , 2002, Pages 70-74

  Ker, Ming Dou ^a   Hsu, Hsin Chyh ^a   Peng, Jeng Jie ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

CMOS integrated circuits; CMOS process; CMOS technology; Current measurement; Electrostatic discharge; Integrated circuit modeling; MOS devices; Robustness; Semiconductor device modeling; Stress

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRIC NETWORK ANALYSIS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; ELECTROSTATICS; FAILURE ANALYSIS; INTEGRATED CIRCUITS; MOS DEVICES; ROBUSTNESS (CONTROL SYSTEMS); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; STRESSES;

CMOS PROCESSS; CMOS TECHNOLOGY; ESD ROBUSTNESS; ESD STRESS; INTEGRATED CIRCUIT MODELING; MACHINE MODELING; MACHINE MODELS; SURFACE CHANNEL;

CMOS INTEGRATED CIRCUITS;

EID: 84948798717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2002.1025614     Document Type: Conference Paper

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