ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2001, Pages 85-90

  Ker, M D ^a   Chuang, C H ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; CMOS INTEGRATED CIRCUITS; COBALT COMPOUNDS; DIODES; ELECTRIC BREAKDOWN; ELECTROSTATICS; HUMAN FORM MODELS; INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION; MOS DEVICES; TRANSMISSION LINE THEORY;

ELECTROSTATIC DISCHARGE IMPLANTATION; HUMAN-BODY-MODEL; MACHINE-MODEL; ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION; SILICIDE-BLOCKING MASK; TRANSMISSION LINE PULSE GENERATOR;

ELECTRIC DISCHARGES;

EID: 0034823704     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Method for fabricating an electrostatic discharge protection circuit
2. Method for ESD protection improvement
3. Static discharge circuit having low breakdown voltage bipolar clamp
4. Electrostatic discharge protection circuit employing MOSFETs having double ESD implantations
5. Photon emission study of ESD protection devices under second breakdown conditions
6. Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks
7. Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process
8. ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven versus substrate-triggered design