Noise-aware buffer planning for interconnect-driven floorplanning

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 423-426

  Li, Shu Min ^a   Cherng, Yih Huai ^b   Chang, Yao Wen ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b SYNOPSYS INC   (United States)

^c NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DATA FLOW ANALYSIS;

BUFFER INSERTION; COUPLING CAPACITANCE; DESIGN CONVERGENCE; INTERCONNECT DELAY; INTERCONNECT OPTIMIZATION; NOISE OPTIMIZATION; POST-LAYOUT OPTIMIZATION; TIMING CONSTRAINTS;

BUFFER CIRCUITS;

EID: 0042693220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195052     Document Type: Conference Paper

References (10)

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