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Volumn 38, Issue 1-2 SPEC. ISS., 1996, Pages 3-31

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

Author keywords

Diode clamps; ESD; Mixed voltage; Protection

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROSTATICS; NETWORKS (CIRCUITS); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DIODES; THERMOELECTRICITY;

EID: 0030264354     PISSN: 03043886     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0304-3886(96)00014-9     Document Type: Article
Times cited : (13)

References (25)
  • 2
    • 0027940828 scopus 로고
    • Low power design: Ways to approach the limits
    • Feb.
    • E.A. Vittoz, Low power design: ways to approach the limits, ISSCC Technical Papers, Feb. 1994, pp. 14-18.
    • (1994) ISSCC Technical Papers , pp. 14-18
    • Vittoz, E.A.1
  • 3
    • 0027969375 scopus 로고
    • Low-voltage CMOS device scaling
    • Feb.
    • C. Hu, Low-voltage CMOS device scaling, ISSCC Technical Papers, Feb. 1994, pp. 86-87.
    • (1994) ISSCC Technical Papers , pp. 86-87
    • Hu, C.1
  • 4
    • 0027881189 scopus 로고
    • Scaling, optimization, and design considerations of electrostatic discharge protection circuits in CMOS technology
    • S. Voldman et al., Scaling, optimization, and design considerations of electrostatic discharge protection circuits in CMOS technology, EOS/ESD Symp. Proc., 1993, pp. 251-260.
    • (1993) EOS/ESD Symp. Proc. , pp. 251-260
    • Voldman, S.1
  • 5
    • 0027797075 scopus 로고
    • ESD sensitivity and VLSI technology trends: Thermal breakdown and dielectric breakdown
    • D. Lin, ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown. EOS/ESD Symp. Proc., 1993, pp. 73-82.
    • (1993) EOS/ESD Symp. Proc. , pp. 73-82
    • Lin, D.1
  • 6
    • 0027883868 scopus 로고
    • Designing on-chip power supply coupling diodes for ESD protection and noise immunity
    • S. Dabral et al., Designing on-chip power supply coupling diodes for ESD protection and noise immunity, EOS/ESD Symp. Proc., 1993, pp. 239-249.
    • (1993) EOS/ESD Symp. Proc. , pp. 239-249
    • Dabral, S.1
  • 9
    • 33747946662 scopus 로고
    • 200 MHz 64-bit dual issue microprocessor
    • D. Dobberpuhl, 200 MHz 64-bit dual issue microprocessor, ISSCC Technical Papers, 1992, pp. 106-107.
    • (1992) ISSCC Technical Papers , pp. 106-107
    • Dobberpuhl, D.1
  • 10
    • 0028754968 scopus 로고
    • Mixed voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technology
    • Session 10.3.1, Dec.
    • S. Voldman and G. Gerosa, Mixed voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technology, Internat. Electron Device Meeting Tech. Digest, Session 10.3.1, Dec. 1994, pp. 277-281.
    • (1994) Internat. Electron Device Meeting Tech. Digest , pp. 277-281
    • Voldman, S.1    Gerosa, G.2
  • 11
    • 0028126178 scopus 로고
    • A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor
    • Paper 12.6, Session 12
    • D. Pham et al., A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor, Paper 12.6, Session 12, ISSCC Tech. Digest, 1994.
    • (1994) ISSCC Tech. Digest
    • Pham, D.1
  • 12
    • 0021629272 scopus 로고
    • Using SCR's as transient protection structures in integrated circuits
    • L. Avery, Using SCR's as transient protection structures in integrated circuits, EOS/ESD Symp. Proc., 1983, pp. 177-180.
    • (1983) EOS/ESD Symp. Proc. , pp. 177-180
    • Avery, L.1
  • 13
    • 0024176693 scopus 로고
    • A process tolerant input protection for advanced CMOS processes
    • R. Rountree et al., A process tolerant input protection for advanced CMOS processes, EOS/ESD Symp. Proc., 1988, pp. 201-205.
    • (1988) EOS/ESD Symp. Proc. , pp. 201-205
    • Rountree, R.1
  • 14
    • 0028742177 scopus 로고
    • ESD protection in a mixed voltage interface and multi-rail disconnected power grid environment in 0.5 and 0.25 μm channel length CMOS technologies
    • S. Voldman, ESD protection in a mixed voltage interface and multi-rail disconnected power grid environment in 0.5 and 0.25 μm channel length CMOS technologies, EOS/ESD Symp. Proc., Sept. 1994.
    • (1994) EOS/ESD Symp. Proc., Sept.
    • Voldman, S.1
  • 15
    • 0041528640 scopus 로고    scopus 로고
    • US Patent #2,663,806, Semiconductor signal translating device, Dec. 22, 1953
    • S. Darlington, US Patent #2,663,806, Semiconductor signal translating device, Dec. 22, 1953.
    • Darlington, S.1
  • 18
    • 28744434587 scopus 로고
    • Retrograde well and epitaxial thickness optimization for shallow and deep trench collar MINT SPT DRAM and CMOS logic technologies
    • S. Voldman et al., Retrograde well and epitaxial thickness optimization for shallow and deep trench collar MINT SPT DRAM and CMOS logic technologies, IEDM Tech. Digest (1992) 811-814.
    • (1992) IEDM Tech. Digest , pp. 811-814
    • Voldman, S.1
  • 19
    • 4244216751 scopus 로고
    • A 0.4-micron fully complementary BiCMOS technology for advanced logic and microprocessor applications
    • S.W. Sun et al., A 0.4-micron fully complementary BiCMOS technology for advanced logic and microprocessor applications, IEDM Tech. Digest (1991) 85-88.
    • (1991) IEDM Tech. Digest , pp. 85-88
    • Sun, S.W.1
  • 20
    • 0016988696 scopus 로고
    • On the proportioning of chip area for multi-stage darlington power transistors
    • C. Wheatley and W. Einthoven, On the proportioning of chip area for multi-stage darlington power transistors, IEEE Trans. Elec. Dev., ED-23 (1976) 870-878.
    • (1976) IEEE Trans. Elec. Dev. , vol.ED-23 , pp. 870-878
    • Wheatley, C.1    Einthoven, W.2
  • 21
    • 35148815587 scopus 로고
    • Pulse power failure modes in semiconductors
    • D. Tasca, Pulse power failure modes in semiconductors, IEEE Trans. Nucl. Sci., NS-17 (1970) 364-372.
    • (1970) IEEE Trans. Nucl. Sci. , vol.NS-17 , pp. 364-372
    • Tasca, D.1
  • 22
    • 0000318215 scopus 로고
    • A new three-dimensional device simulation formulation
    • E. Buturla, J. Johnson, S. Furkay and P. Cottrell, A new three-dimensional device simulation formulation, NASECODE VI (1989) pp. 291-296.
    • (1989) NASECODE , vol.6 , pp. 291-296
    • Buturla, E.1    Johnson, J.2    Furkay, S.3    Cottrell, P.4
  • 23
    • 0028734432 scopus 로고
    • Three-dimensional electrothermal simulation of electrostatic discharge protection circuits
    • S. Voldman, S. Furkay and J. Slinkman, Three-dimensional electrothermal simulation of electrostatic discharge protection circuits. EOS/ESD Symp. Proc., Sept. 1994.
    • (1994) EOS/ESD Symp. Proc., Sept.
    • Voldman, S.1    Furkay, S.2    Slinkman, J.3
  • 24
    • 0043031549 scopus 로고
    • Technology Modelling Associates, Palo Alto, CA
    • TSUPREME-4 Users Manual, Technology Modelling Associates, Palo Alto, CA, 1995.
    • (1995) TSUPREME-4 Users Manual
  • 25
    • 0025512595 scopus 로고
    • Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modelling
    • G. Wachutka, Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modelling, IEEE Trans. Computer Aided Des., 9 (1990) 1141-1149.
    • (1990) IEEE Trans. Computer Aided Des. , vol.9 , pp. 1141-1149
    • Wachutka, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.