Global and local congestion optimization in technology mapping

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 498-506

  Pandini, Davide ^a   Pileggi, Lawrence T ^b   Strojwas, Andrzej J ^b  

^a STMICROELECTRONICS   (Italy)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Congestion estimation; Logic synthesis; Physical design placement; Routability; Routing; Technology mapping; Wiring congestion

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; GRAPH THEORY; HEURISTIC METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION;

CONGESTION ESTIMATION; LOGIC SYNTHESIS; PHYSICAL DESIGN; PLACEMENT; ROUTABILITY; ROUTING; WIRING CONGESTION;

LOGIC DESIGN;

EID: 0037389455     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809646     Document Type: Article

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