Understanding and addressing the impact of wiring congestion during technology mapping

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 131-136

  Pandini, Davide ^a   Pileggi, Lawrence T ^a   Strojwas, Andrzej J ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

Algorithms; Design; Performance

Indexed keywords

ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTIMIZATION; ROUTERS;

TECHNOLOGY MAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0036375850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505418.505421     Document Type: Conference Paper

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