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Volumn , Issue , 1999, Pages 531-536

Wavefront technology mapping

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL MAPPING; DELAY MODELING; DIRECTED ACYCLIC GRAPHS; DYNAMIC DECOMPOSITION; EFFICIENT IMPLEMENTATION; TECHNOLOGY MAPPING; TECHNOLOGY MAPPING ALGORITHMS; WAVEFRONT ALGORITHMS;

EID: 84893635702     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761178     Document Type: Conference Paper
Times cited : (24)

References (14)
  • 4
    • 84989495069 scopus 로고
    • Timing verification and the timing analysis program
    • Las Vegas, June
    • R. HitchcockSr. Timing verification and the timing analysis program. In ACM IEEE Nineteenth Design Automation Conference, pages 594-604, Las Vegas, June 1982.
    • (1982) ACM IEEE Nineteenth Design Automation Conference , pp. 594-604
    • Hitchcocksr, R.1
  • 6
    • 0023210698 scopus 로고
    • Dagon: Technology binding and local optimization by dag matching
    • June
    • K. Keutzer. Dagon: Technology binding and local optimization by dag matching. In Proc of the 24th Design Automation Conference, pages 341-347, June 1987.
    • (1987) Proc of the 24th Design Automation Conference , pp. 341-347
    • Keutzer, K.1
  • 7
    • 0003254358 scopus 로고    scopus 로고
    • Continuous optimizations in synthesis: The discretization problem
    • June
    • P. Kudva. Continuous optimizations in synthesis: The discretization problem. In Proc of Int. Workshop on Logic Synthesis, pages 408-419, June 1998.
    • (1998) Proc of Int. Workshop on Logic Synthesis , pp. 408-419
    • Kudva, P.1
  • 9
  • 11
    • 0003623384 scopus 로고
    • Technical report, University of California, Berkeley
    • R. Rudell. Logic synthesis for vlsi design. Technical report, University of California, Berkeley, 1989.
    • (1989) Logic Synthesis for Vlsi Design
    • Rudell, R.1
  • 12
    • 0031175711 scopus 로고    scopus 로고
    • Design methodology for the s/390 parallel enterprise server g4 microprocessors
    • July/September
    • K. Shepard and et al. Design methodology for the s/390 parallel enterprise server g4 microprocessors. IBM J. Res. Develop., 41(4/5):515-547, July/September 1997.
    • (1997) IBM J. Res. Develop. , vol.41 , Issue.4-5 , pp. 515-547
    • Shepard, K.1
  • 13
    • 0030189111 scopus 로고    scopus 로고
    • Booledozer logic synthesis for asics
    • July
    • L. Stok and et al. Booledozer logic synthesis for asics. IBM J. Res. and Develop., Vol. 40(4):407-430, July 1996.
    • (1996) IBM J. Res. and Develop. , vol.40 , Issue.4 , pp. 407-430
    • Stok, L.1
  • 14
    • 0003275249 scopus 로고
    • The theory of logical effort: Desiging for speed on the back of an envelope
    • University of California at Santa Cruz
    • I. Sutherland and R. Sproull. The theory of logical effort: Desiging for speed on the back of an envelope. In Advanced Research in VLSI, University of California at Santa Cruz, 1991.
    • (1991) Advanced Research in VLSI
    • Sutherland, I.1    Sproull, R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.