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2001 International Workshop on System-Level Interconnect Prediction (SLIP 2001)

Volumn , Issue , 2001, Pages 91-98

On the relevance of wire load models

(3) Boese, Kenneth D a Kahng, Andrew B b Mantik, Stefanus c

a CADENCE DESIGN SYSTEMS (United States)

b UNIVERSITY OF CALIFORNIA (United States)

c Los Angeles (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

WIRE LOAD MODELS (WLM);

ELECTRIC WIRE;

EID: 0035789302 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1145/368640.368719 Document Type: Conference Paper

Times cited : (13)

References (9)

1
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- Boese, K.D.¹ Kahng, A.B.² McCoy, B.A.³ Robins, G.⁴

2
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- Fidelity and near-optimality of elmore-based routing constructions
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- Boese, K.D.¹ Kahng, A.B.² McCoy, B.A.³ Robins, G.⁴

3
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- Pre-layout estimation of individual wire lengths
- April
- S. Bodapati and F. N. Najm, "Pre-Layout Estimation of Individual Wire Lengths", ACM Intl. Workshop on System-Level Interconnect Prediction, April 2000, pp. 93-98.
- (2000) ACM Intl. Workshop on System-Level Interconnect Prediction , pp. 93-98
- Bodapati, S.¹ Najm, F.N.²

4
- 0029213552
- Quantified suboptimality of VLSI layout heuristics
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- (1995) Proc. ACM/IEEE Design Automation Conf. , pp. 216-221
- Hagen, L.¹ Huang, J.H.² Kahng, A.B.³

5
- 0032715195
- Improved effective capacitance computations for use in logic and layout optimization
- A. B. Kahng and S. Muddu, "Improved Effective Capacitance Computations for Use in Logic and Layout Optimization", Proc. IEEE Intl. Conf. on VLSI Design, 1999, pp. 578-582.
- (1999) Proc. IEEE Intl. Conf. on VLSI Design , pp. 578-582
- Kahng, A.B.¹ Muddu, S.²

6
- 0012955349
- Synopsys, Inc., Liberty User Guide, Version 1999, 1999.
- (1999) Liberty User Guide, Version 1999

7
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- Combining technology mapping with post-placement resynthesis for performance optimization
- October
- A. Lu, H. Eisenmann, G. Stenz and F. M. Johannes, "Combining technology mapping with post-placement resynthesis for performance optimization", Proc. Intl. Conf. on Computer Design, October 1998, pp. 616-621.
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- Lu, A.¹ Eisenmann, H.² Stenz, G.³ Johannes, F.M.⁴

8
- 0034592340
- Why interconnect prediction doesn't work
- April
- L. Scheffer and E. Nequist, "Why Interconnect Prediction Doesn't Work", ACM Intl. Workshop on System-Level Interconnect Prediction, April 2000, pp. 139-144.
- (2000) ACM Intl. Workshop on System-Level Interconnect Prediction , pp. 139-144
- Scheffer, L.¹ Nequist, E.²

9
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- San Francisco, Morgan Kaufmann
- I. Sutherland, R. Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits, San Francisco, Morgan Kaufmann, 1999.
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- Sutherland, I.¹ Sproull, R.² Harris, D.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.