A system-level solution to domino synthesis with 2 GHz application

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 164-171

  Chappell, B ^a   Wang, X ^a   Patra, P ^a   Saxena, P ^a   Vendrell, J ^a   Gupta, S ^a   Varadarajan, S ^a   Gomes, W ^a   Hussain, S ^a   Krishnamurthy, H ^a   Venkateshmurthy, M ^a   Jain, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC GATES; OPTIMIZATION;

DOMINO SYNTHESIS; SILICON-READY LAYOUT; STATE-ACCURATE LOGIC;

COMPUTER AIDED LOGIC DESIGN;

EID: 0036397195     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106765     Document Type: Article

References (11)

1. M. Zhao, S. Sapatnekar, "Technology Mapping for Domino Logic," ICCAD 1998.
2. G. Yee, C. Sechen, "Dynamic Logic Synthesis," CICC 1997.
3. M. Prasad, et al., "Domino Synthesis and Technology Mapping," IWLS 1997.
4. M. Zhao, S. Sapatnekar, "Timing Optimization of Mixed Static and Domino Logic," ISCAS 1998.
5. R.K. Brayton, et al, "MIS: A Multiple-Level Logic Optimization System," IEEE TCAD, Vol 5, No. 6, 1987.
6. P. Patra, U. Narayanan, "Phase Assignment for Synthesis of Low Power Domino Circuits," DAC 1999.
7. X. Wang, P. Sawkar, B. Chappell, "A Constructive Matching Algorithm for Library-Based Domino Technology Mapping," IWLS 2002.
8. J. P. Fishburn, A. E. Dunlop, "TILOS: A Posynomial Programming Approach to Transistor Sizing," ICCAD 1985.
9. O.C. Martin, S.W. Otto, "Combining Simulated Annealing with Local Search Heuristics", Annals of Op. Research, v63, 1996.
10. P. Saxena, S. Gupta, "Shield Count Minimization in Congested Regions," ISPD 2002.
11. K.D. Boese, A.B. Kahng, S. Mantik, "On the Relevance of Wire Load Models," SLIP 2001.