Formulae and applications of interconnect estimation considering shield insertion and net ordering

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 327-332

  Ma, James D Z ^a   He, Lei ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL INTEGRATED CIRCUITS; ROUTERS; VLSI CIRCUITS;

INTERCONNECT ESTIMATION; NET ORDERING; SHIELD ESTIMATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035212465     PISSN: 10923152     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCAD.2001.968641     Document Type: Article

References (18)

1. Minimum crosstalk switchbox routing
2. Post global routing crosstalk synthesis
3. Crosstalk reduction for VLSI
4. Buffer insertion for noise and delay optimization
5. A novel VLSI layout fabric for deep sub-micron applications
6. An efficient inductance modeling for on-chip interconnects
7. IC analyses including extracted inductance model
8. Effects of global interconnect optimizations on performance estimation of deep submicron design
9. Simultaneous shielding insertion and net ordering for capacitive and inductive coupling minimization
10. Simultaneous shield insertion and net ordering for coupled RLC nets under explicit noise constraint
11. Equivalent circuit models for three-dimensional multiconductor systems
12. eff model
13. When are transmission-line effects important for on-chip wires
14. Figures of merit to characterize the importance of on-chip inductance
15. Interconnect design for deep submicron ICs