Pre-route noise estimation in deep submicron integrated circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 413-418

  Becer, M R ^a   Blaauw, D ^b   Panda, R ^a   Hajj, I N ^c  

^a MOTOROLA INC   (United States)

^b University of Michigan   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Added delay; Capacitance; Data mining; Failure analysis; Information analysis; Integrated circuit noise; Microprocessors; Routing; Time to market; Wires

Indexed keywords

CAPACITANCE; COMMERCE; CONCURRENT ENGINEERING; DESIGN; FAILURE ANALYSIS; INFORMATION ANALYSIS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; WIRE;

ADDED DELAY; CAPACITANCE EXTRACTION; COUPLING CAPACITANCE; HIGH-PERFORMANCE MICROPROCESSORS; INTEGRATED CIRCUIT NOISE; PROBABILISTIC METHODS; ROUTING; TIME TO MARKET;

DATA MINING;

EID: 0742328299     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996781     Document Type: Conference Paper

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