Behavioral-level DFT via formal operator testability measures

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 6, 2002, Pages 595-611

  Seshadri, Sandhya ^a   Hsiao, Michael S ^b  

^a INTEL CORPORATION   (United States)

^b State University   (United States)

Author keywords

Behavioral level; DFT; Operator testability; SSA representation; Value range

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DATA FLOW ANALYSIS; ELECTRIC NETWORK SYNTHESIS; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT TESTING;

AUTOMATIC TEST PATTERN GENERATION; BEHAVIORAL DESCRIPTION; FORMAL OPERATOR; OPERATOR TESTABILITY; REGISTER TRANSFER LEVEL; STATIC SINGLE ASSIGNMENT;

DESIGN FOR TESTABILITY;

EID: 0036919762     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1020849006472     Document Type: Article

References (23)

1. S. Bhatia and N.K. Jha, "Genesis: A Behavioral Synthesis System for Hierarchical Testability," in Proc. European Design and Test Conf., 1994, pp. 272-276.
2. S. Bhatia and N. K. Jha, "Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches," in Proc. Int'l. Conf. on Computer Design, 1994, pp. 91-96.
3. S.T. Chakradhar, A. Balakrishnan, and V.D. Agrawal, "An Exact Algorithm for Selecting Partial Scan Flip-Flops," in Proc. Design Automation Conf., 1994, pp. 81-86.
4. R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck, "Efficiently Computing SSA and the Control Dependence Graph," ACM Trans. Programming Lang. and Systems, vol. 13, no. 4, pp. 451-490, Oxtober 1991.
5. I. Ghosh, A. Raghunathan, and N.K. Jha, "Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis," in Proc. Int'l. Conf. on Computer Design, 1995, pp. 173-179.
6. 1991 High Level Synthesis Benchmarks, Digital Design Environments Laboratory, University of Cincinnati, available at www.ececs.uc.edu/ ddel/projects/mss/benchmarks.
7. 1992 High-Level Synthesis Workshop Benchmarks, available at www.ics.uci.edu/pub/HLSynth91.
8. 1995 High-Level Synthesis Workshop Benchmarks, available at www.ics.uci.edu/pub/HLSynth95.
9. M.S. Hsiao, G.S. Saund, E.M. Rudnick, and J.H. Patel, "Partial Scan Selection Based on Dynamic Reachability and Observability Information," in Proc. Int'l. Conf. on VLSI Design, 1998, pp. 174-180.
10. F.F. Hsu, "High-Level Testability Analysis and Enhancement for Digital Systems," Ph.D Dissertation, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, October 1998.
11. F.F. Hsu, E.M. Rudnick, and J.H. Patel, "Enhancing High-Level Control-Flow for Improved Testability," in Proc. Int'l. Conf. on Computer-Aided Design, 1996, pp. 322-328.
12. K. Knobe and V. Sarkar, "Array SSA Form and its Use in Parallelization," in Proc. ACM SIGPLAN-SIGACT Symposium on Principles of Programming Lang., pp. 107-120, January 1998.
13. T.C. Lee, N.K. Jha, and W.H. Wolf, "Behavioral Synthesis of Highly Testable Data Paths Under Non-Scan and Partial-Scan Environments," in Proc. Design Automation Conf., 1993, pp. 292-297.
14. N. Mukherjee et al., "Arithmetic Built-in Self Test for High-Level Synthesis," in Proc. VLSI Test Symp., 1995, pp. 132-139.
15. K.A. Ockunzzi and C.A. Papachristou, "Testability Enhancement for Behavioral Descriptions Containing Conditional Statements," in Proc. Int'l. Test Conf., 1997, pp. 236-245.
16. P.S. Parikh and M. Abramovici, "Testability-Based Partial Scan Analysis," Journal of Electronic Testing: Theory and Applications, vol. 7, pp. 61-70, August 1995.
17. J.R.C. Patterson, "Accurate Static Branch Prediction by Value Range Propagation," in Proc. Conf. on Programming Lang. Design and Implementation, 1995, pp. 67-78.
18. S. Seshadri and M.S. Hsiao, "An Integrated Approach to High-Level Design-for-Testability Using Value-Range and Variable Testability Techniques," in Proc. Int'l. Test Conf., 1999, pp. 858-867.
19. S. Seshadri and M.S. Hsiao, "Formal Value-Range and Variable Testability Techniques for High-Level Design-for-Testability," Journal of Electronic Testing: Theory and Applications, vol. 16, pp. 131-145, February 2000.
20. S. Seshadri and M.S. Hsiao, "Formal Operator Testability Methods for Behavioral-Level DFT Using Value Ranges," in Proc. Int'l. Workshop on High Level Design Validation and Test, pp. 105-111, November 2000.
21. M. Takahashi, R. Sakurai, H. Noda, and T. Kambe, "A Testability Analysis Method for Register-Transfer Level Description," in Proc. Asia-South-Pacific Design Automation Conf., 1997, pp. 307-312.
22. P.A. Thaker, V.D. Agrawal, and M.E. Zaghloul, "Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test," in Proc. VLSI Test Symp., 1999, pp. 182-188.
23. M.N. Wegman and F.K. Zadeck, "Constant Propagation with Conditional Branches," ACM Trans. Programming Lang and Systems, vol. 13, no. 2, pp. 181-210, April 1991.