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Volumn , Issue , 1997, Pages 307-312
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Testability analysis method for register-transfer level descriptions
a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
COST EFFECTIVENESS;
DATA TRANSFER;
INTEGRATED CIRCUIT TESTING;
LOGIC GATES;
DESIGN FOR TESTABILITY (DFT);
REGISTER TRANSFER LEVEL (RTL);
INTEGRATED CIRCUIT LAYOUT;
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EID: 0030672603
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (6)
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References (6)
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