Formal value-range and variable testability techniques for high-level design-for-testability

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 1-2, 2000, Pages 131-145

  Seshadri, Sandhya ^a   Hsiao, Michael S ^b,c,d  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b RUTGERS UNIVERSITY   (United States)

^c NEC LABORATORIES AMERICA   (United States)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROLLABILITY; DATA FLOW ANALYSIS; DESIGN FOR TESTABILITY; GRAPH THEORY; OBSERVABILITY;

CIRCUIT BEHAVIORAL LEVEL; CONTROL DATA FLOW GRAPH; REGISTER TRANSFER LEVEL;

INTEGRATED CIRCUIT TESTING;

EID: 0034140108     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008357211476     Document Type: Article

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