Formal operator testability methods for behavioral-level DFT using value ranges

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 105-111

  Seshadri, S ^a   Hsiao, M S ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b RUTGERS UNIVERSITY   (United States)

Author keywords

Analytical models; Circuit synthesis; Circuit testing; Computational modeling; Computer graphics; Data analysis; Electric variables control; Input variables; Performance analysis; Performance evaluation

Indexed keywords

ANALYTICAL MODELS; COMPUTER GRAPHICS; DATA FLOW ANALYSIS; DATA REDUCTION; DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRIC VARIABLES CONTROL; SYNTHESIS (CHEMICAL);

CIRCUIT SYNTHESIS; CIRCUIT TESTING; COMPUTATIONAL MODEL; INPUT VARIABLES; PERFORMANCE ANALYSIS; PERFORMANCE EVALUATION;

DESIGN FOR TESTABILITY;

EID: 0012142641     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889569     Document Type: Conference Paper

References (20)

1. S. Bhatia and N.K. Jha. "Genesis: a behavioral synthesis system for hierarchical testability," Proc. European Design and Test Conf., pp. 272-276, 1994.
2. I. Ghosh, A. Raghunathan and N.K. Jha. "Design for hierarchical testability of RTL circuits obtained by behavioral synthesis," Proc. Intl. Conf. Computer Design, pp. 173-179, 1995.
3. S. Bhatia and N.K. Jha. "Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches," Proc. Intl. Conf. on Computer Design, pp. 91-96, 1994.
4. T.C. Lee, N.K. Jha and W.H. Wolf. "Behavioral synthesis of highly testable data paths under non-scan and partial-scan environments," Proc. Design Automation Conf., pp. 292-297, 1993.
5. F.F. Hsu, E.M. Rudnick and J.H. Patel "Enhancing High-Level Control-Flow for Improved Testability," Proc. Intl. Conf. Computer-Aided Design, pp. 322-328, 1996.
6. P.S. Parikh and M. Abramovici. "Testability-based partial scan analysis," Journal of Electronic Testing: Theory and Applications, vol. 7, August 1995, pp. 61-70.
7. S.T. Chakradhar, A. Balakrishnan and V.D.Agrawal. "An exact algorithm for selecting partial scan flip-flops," Proc. Design Automation Conf., pp. 81-86, 1994.
8. M.S. Hsiao, G.S. Saund, E.M. Rudnick and J.H.Patel. "Partial scan selection based on dynamic reachability and observability information," Proc. Intl. Conf. VLSI Design, pp. 174-180, 1998.
9. F.F. Hsu. "High-level testability analysis and enhancement for digital systems," Ph.D. Dissertation, Univ. of Illinois at Urbana-Champaign, October, 1998.
10. J.R.C. Patterson. "Accurate static branch prediction by value range propagation," Proc. Conf. Programming Lang. Design and Implementation, pp. 67-78, 1995.
11. M.N. Wegman and F.K. Zadeck. "Constant Propagation with Conditional Branches," ACM Trans. Programming Lang. & Systems, 13(2), April 1991, pp. 181-210.
12. S. Ravi, G. Lakshminarayana, and N. K. Jha. "TAO: Regular expression based high-level testability analysis and optimization," Proc. Intl. Test Conf., pp. 331-340, 1998.
13. N. Mukherjee et al. "Arithmetic built-in self test for high-level synthesis," IEEE VTS 1995.
14. R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman and F.K. Zadeck. "Efficiently Computing SSA and the Control Dependence Graph," ACM Trans. on Programming Lang. & Systems, 13(4), Oct 1991, pp. 451-490.
15. M. Takahashi, et al. "A Testability Analysis Method for Register-Transfer Level Description," Proc. ASP-Design Automation Conf., pp. 307-312, 1997.
16. K. Knobe and V. Sarkar. "Array SSA Form and its use in Parallelization," Proc. ACM SIGPLAN-SIGACT Symposium on Principles of Programming Lang., Jan 1998.
17. K. A. Ockunzzi and C. A. Papachristou. "Testability Enhancement for Behavioral Descriptions Containing Conditional Statements," Proc. Intl. Test Conf., pp. 236-245, 1997.
18. S. Seshadri and M.S. Hsiao. "An Integrated Approach to High-Level Design-For-Testability Using Value-Range and Variable Testability Techniques," Proc. Intl. Test Conf., pp. 858-867, 1999.
19. 1992 High-Level Synthesis Workshop Benchmarks, www.ics.uci.edu/pub/HLSynth92.
20. 1995 High-Level Synthesis Workshop Benchmarks, www.ics.uci.edu/pub/HLSynth95.