Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1995, Pages 173-179

  Ghosh, Indradeep ^a   Raghunathan, Anand ^a   Jha, Niraj K ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONTROLLABILITY; CRITICAL PATH ANALYSIS; DATA HANDLING; DATA TRANSFER; FOURIER TRANSFORMS; HIERARCHICAL SYSTEMS; OBSERVABILITY; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS;

BEHAVIORAL SYNTHESIS; CONTROL DATA FLOW GRAPH; GATE-LEVEL SEQUENTIAL TEST GENERATION; HIERARCHICAL TESTABILITY; HIGH LEVEL SYNTHESIS; RTL CIRCUITS;

COMPUTER CIRCUITS;

EID: 0029506902     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)