A built-in self-test scheme with diagnostics support for embedded SRAM

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 6, 2002, Pages 637-647

  Wang, Chih Wea ^a   Wu, Chi Feng ^a   Li, Jin Fu ^a   Wu, Cheng Wen ^a   Teng, Tony ^b   Chiu, Kevin ^b   Lin, Hsiao Ping ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

Memory BIST; Memory diagnostics; Memory testing; RAM; Semiconductor memory

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER PROGRAMMING; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; STATIC RANDOM ACCESS STORAGE;

AUTOMATIC DIAGNOSTIC SYSTEM; EMBEDDED MEMORY; MEMORY DIAGNOSTICS; MEMORY TESTING; SEMICONDUCTOR MEMORY; SYSTEM ON CHIP;

BUILT-IN SELF TEST;

EID: 0036910672     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1020805224219     Document Type: Article

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