Error catch and analysis for semiconductor memories using March tests

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 468-471

  Wu, Chi Feng ^a   Huang, Chih Tsun ^a   Wang, Chih Wea ^a   Cheng, Kuo Liang ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; ERRORS; SEMICONDUCTOR STORAGE; ERROR ANALYSIS; RANDOM ACCESS STORAGE; RELIABILITY;

DIAGNOSTIC RESOLUTION; ERROR LOCATION; FAULT SIMULATORS; MARCH ALGORITHM; MEMORY UNDER TESTS; RELIABILITY IMPROVEMENT; SEMICONDUCTOR MEMORY; TEST ALGORITHMS;

RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE;

ERROR CATCH AND ANALYSIS; MARCH TESTS; SEMICONDUCTOR MEMORIES;

EID: 0034477890     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896516     Document Type: Conference Paper

References (8)

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