Design rewiring for power minimization

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Amiri, Mandana ^a   Veneris, Andreas ^a   Ting, Ivor ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR DETECTION; LOGIC CIRCUITS; OPTIMIZATION; POWER CONTROL; SWITCHING SYSTEMS;

DESIGN REWIRING; LOGIC OPTIMIZATION; POWER MINIMIZING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0036292894     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Logic verification via test generation
2. An implicit enumeration algorithm to generate test for combinational circuits
3. Perturb and simplify: Multi-level boolean network optimizer
4. Statistical estimation of switching activity in digital circuits
5. Gate-level synthesis for low-power using new transformations
6. Reducing power dissipation after technology mapping by structural transformations
7. Sequential circuit design using synthesis and optimization
8. Design rewiring based on diagnosis techniques
9. Design error diagnosis and correction via test vector simulation
10. Multi-level optimization for low power using local logic transformations