Design rewiring based on diagnosis techniques

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 479-484

  Veneris, A ^a   Abadir, M S ^b   Ting, I ^c  

^a UNIVERSITY OF TORONTO   (Canada)

^b MOTOROLA INC   (United States)

^c Alcatel Corporation   (Canada)

Author keywords

Algorithm design and analysis; Circuit noise; Combinational circuits; Contracts; Design optimization; Error correction; Logic circuits; Logic design; Very large scale integration; Wire

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; CONTRACTS; DESIGN; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; LOGIC DESIGN; LOGIC SYNTHESIS; VLSI CIRCUITS; WIRE;

ALGORITHM DESIGN AND ANALYSIS; CIRCUIT NOISE; CORRECTION TECHNIQUES; DESIGN ERRORS; DESIGN OPTIMIZATION; DIAGNOSIS TECHNIQUES; LOGIC OPTIMIZATION; VLSI DESIGN;

LOGIC CIRCUITS;

EID: 0003100806     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913354     Document Type: Conference Paper

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