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Volumn 2001-January, Issue , 2001, Pages 467-472

Functional extension of structural logic optimization techniques

Author keywords

Automatic test pattern generation; Boolean functions; Computer networks; Electronic mail; Iterative methods; Logic; Optimization methods; Sufficient conditions; Testing; Wire

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; BOOLEAN FUNCTIONS; COMPUTATION THEORY; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; ELECTRONIC MAIL; ITERATIVE METHODS; LOGIC SYNTHESIS; TESTING; WIRE;

EID: 84949812587     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913352     Document Type: Conference Paper
Times cited : (3)

References (10)
  • 1
    • 0027867675 scopus 로고
    • Sequential Logic Optimization by Redundancy Addition and Removal
    • November
    • K.-T. Cheng, L. Entrena. "Sequential Logic Optimization by Redundancy Addition and Removal". Proc. ICCAD, p. 310-315. November, 1993
    • (1993) Proc. ICCAD , pp. 310-315
    • Cheng, K.-T.1    Entrena, L.2
  • 2
    • 0029344148 scopus 로고
    • Combinational and Sequential Logic Optimization by Redundancy Addition and Removal
    • L. A. Entrena, K.-T. Cheng. "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal". IEEE Transactions on CAD, vol.14, n. 7, p. 909-916. 1995.
    • (1995) IEEE Transactions on CAD , vol.14 , Issue.7 , pp. 909-916
    • Entrena, L.A.1    Cheng, K.-T.2
  • 4
    • 0030379797 scopus 로고    scopus 로고
    • Perturb and Simplify: Multilevel Boolean Network Optimizer
    • November
    • S. C. Chang, M. Marek-Sadowska, K.-T. Cheng. "Perturb and Simplify: Multilevel Boolean Network Optimizer". IEEE Transactions on CAD, vol. 15, no 12, p. 1494-1504. November 1996.
    • (1996) IEEE Transactions on CAD , vol.15 , Issue.12 , pp. 1494-1504
    • Chang, S.C.1    Marek-Sadowska, M.2    Cheng, K.-T.3
  • 5
    • 0028698729 scopus 로고
    • Multi-Level Logic Optimization by Implication Analysis
    • Nov.
    • W. Kunz, P. Menon. "Multi-Level Logic Optimization by Implication Analysis". Proc. ICCAD-94, p.6-13. Nov.1994
    • (1994) Proc. ICCAD-94 , pp. 6-13
    • Kunz, W.1    Menon, P.2
  • 7
    • 0028056670 scopus 로고
    • Introduction of permissible bridges with application to logic optimization after technology mapping
    • February
    • B. Rohfleisch, F. Brglez. "Introduction of permissible bridges with application to logic optimization after technology mapping". Proc. European Design & Test Conference (ED&TC), p. 87-93. February 1994.
    • (1994) Proc. European Design & Test Conference (ED&TC) , pp. 87-93
    • Rohfleisch, B.1    Brglez, F.2
  • 8
    • 0029213718 scopus 로고
    • Logic Clause Analysis for Delay Optimization
    • June
    • B. Rohfleisch, B. Wurth, K. Antreich. "Logic Clause Analysis for Delay Optimization". Proc. 32nd DAC, p. 668-672. June 1995.
    • (1995) Proc. 32nd DAC , pp. 668-672
    • Rohfleisch, B.1    Wurth, B.2    Antreich, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.