Evaluation of mechanical stresses in silicon substrates due to lead-tin solder bumps via synchrotron X-ray topography and finite element modeling

Microelectronic Engineering

Volumn 65, Issue 1-2, 2002, Pages 209-221

  Kanatharana, J ^a   Perez Camacho J J ^b   Buckley, T ^b   McNally, P J ^a   Tuomi, T ^c   Danilewsky, A N ^d   O'Hare, M ^a   Lowney, D ^a   Chen, W ^a   Rantamaki R ^c   Knuuttila, L ^c   Riikonen, J ^c  

^a DUBLIN CITY UNIVERSITY   (Ireland)

^b Leixlip House Hotel   (Ireland)

^c AALTO UNIVERSITY   (Finland)

^d NONE

Author keywords

Ball grid array; Finite element modeling; Flip chip; Stress; X ray topography

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; SILICON WAFERS; STRAIN; STRESSES; X RAY ANALYSIS;

SYNCHROTRON X-RAY TOPOGRAPHY (SXRT);

SEMICONDUCTING SILICON;

EID: 0036891847     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(02)00852-3     Document Type: Article

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