Structural approach for space compaction for concurrent checking and BIST

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 354-361

  Seuring, M ^a   Gossel, M ^a   Sogomonyan, E ^a  

^a UNIVERSITY OF POTSDAM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; EFFICIENCY; ERROR DETECTION; ESTIMATION; FLOWCHARTING; INTEGRATED CIRCUIT TESTING; PROBABILITY;

CONCURRENT CHECKING;

VLSI CIRCUITS;

EID: 0032316475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)