High-level test generation using physically-induced faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1995, Pages 20-28

  Hansen, Mark C ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT UNDER TEST; HIGH LEVEL TEST GENERATION; PHYSICALLY INDUCED FAULTS; SINGLE STUCK LINE;

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COMPUTER SOFTWARE; FAILURE ANALYSIS; LOGIC DESIGN; LOGIC GATES;

PRINTED CIRCUIT TESTING;

EID: 0029213805     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)