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Volumn , Issue , 2000, Pages 638-643
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Using on-chip test pattern compression for full scan SoC designs
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Author keywords
[No Author keywords available]
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Indexed keywords
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
BUILT-IN SELF TEST;
CMOS INTEGRATED CIRCUITS;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
DESIGN FOR TESTABILITY;
ELECTRIC POWER SUPPLIES TO APPARATUS;
MICROCONTROLLERS;
MICROPROCESSOR CHIPS;
SHIFT REGISTERS;
AUTOMATIC TEST PATTERN GENERATION TOOL;
MULTIPLE INPUT SHIFT REGISTER;
ON-CHIP TEST PATTERN COMPRESSION;
SYSTEM-ON-CHIP;
VERILOG PROGRAMMING LANGUAGE;
INTEGRATED CIRCUIT TESTING;
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EID: 0034482666
PISSN: 10893539
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
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Times cited : (4)
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References (3)
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