Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors

IEEE Transactions on Reliability

Volumn 45, Issue 3, 1996, Pages 404-412

  Karri, Ramesh ^a   Orailoglu, Alex ^b  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Fault security; Faulttolerance; Vlsi architecture; Vlsi synthesis

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL SIGNAL PROCESSING; ERROR DETECTION; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; RELIABILITY; SCHEDULING; VLSI CIRCUITS;

COMPUTER AIDED BEHAVIORAL SYNTHESIS; FAULT SECURE MICROARCHITECTURES;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030245132     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/24.536993     Document Type: Article

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