-
1
-
-
78751619530
-
Eficient use of time and hardware re-dundancy for concurrent error detection in a 32-bit VLSI adder
-
Barry W. Johnson, James H. Aylor, and Haytham H. Hana, "Eficient use of time and hardware re-dundancy for concurrent error detection in a 32-bit VLSI adder, " IEEE Journal of Solid-State Circuits, vol. 23, pp. 208-215, 1988.
-
(1988)
IEEE Journal of Solid-State Circuits
, vol.23
, pp. 208-215
-
-
Johnson, B.W.1
Aylor, J.H.2
Hana, H.H.3
-
6
-
-
85040362557
-
FFT arrays with built-in error correction
-
Yuang-Ming Hsu and Earl E. Swartzlander, Jr., "FFT arrays with built-in error correction, " Proc. 28th Asilomar Conference on Signals, Systems, and Computers, pp. 172-176, 1994.
-
(1994)
Proc. 28th Asilomar Conference on Signals Systems and Computers
, pp. 172-176
-
-
Hsu, Y.1
Earl, E.S.2
-
8
-
-
0014837586
-
On division by functional iteration
-
Michael J. Flynn, "On division by functional iteration, " IEEE Transactions on Computers, vol. C-19, pp. 702-706, 1970.
-
(1970)
IEEE Transactions on Computers
, vol.19
, pp. 702-706
-
-
Michael, J.1
Flynn2
-
9
-
-
0003735029
-
A division method using a parallel multiplier
-
Domenico Ferrari, "A division method using a parallel multiplier, " IEEE Transactions on Electronic Computers, vol. EC-16, pp. 224-226, 1967.
-
(1967)
IEEE Transactions on Electronic Computers
, vol.16
, pp. 224-226
-
-
Ferrari, D.1
-
12
-
-
0013235901
-
The IBM system/360 model 91: Floating-point execution unit
-
S. F. Anderson, J. G. Earle, R. E. Goldschmidt, and D. M. Powers, "The IBM System/360 Model 91: Floating-point execution unit, " IBM Journal of Research and Development, vol. 11, pp. 34-53, 1967.
-
(1967)
IBM Journal of Research and Development
, vol.11
, pp. 34-53
-
-
Anderson, S.F.1
Earle, J.G.2
Goldschmidt, R.E.3
Powers, D.M.4
-
13
-
-
0025228329
-
Computation of elementary functions on the IBM RISC System/6000 processor
-
Peter. W. Markstein, "Computation of elementary functions on the IBM RISC System/6000 processor, " IBM Journal of Research and Development, vol. 34, pp. 111-119, 1990.
-
(1990)
IBM Journal of Research and Development
, vol.34
, pp. 111-119
-
-
Peter, W.1
Markstein2
-
14
-
-
0028342274
-
Accurate rounding scheme for the Newton-Raphson method us-ing redundant binary arithmetic
-
Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, and Shigeo Kuninobu, "Accurate rounding scheme for the Newton-Raphson method us-ing redundant binary arithmetic, " IEEE Transactions on Computers, vol. 43, pp. 43-51, 1994.
-
(1994)
IEEE Transactions on Computers
, vol.43
, pp. 43-51
-
-
Kabuo, H.1
Taniguchi, T.2
Miyoshi, A.3
Yamashita, H.4
Urano, M.5
Edamatsu, H.6
Kuninobu, S.7
-
15
-
-
0028550319
-
Division unit with Newton-raphson approximation and digit-by-digit renement of the quotient
-
P. Montuschi, L. Ciminiera, and A. Guistina, "Division unit with Newton-Raphson approximation and digit-by-digit renement of the quotient, " IEE Proceedings: Computers and Digital Techniques, vol. 141, pp. 317-324, 1994.
-
(1994)
IEE Proceedings: Computers and Digital Techniques
, vol.141
, pp. 317-324
-
-
Montuschi, P.1
Ciminiera, L.2
Guistina, A.3
-
17
-
-
84866069516
-
Reduced area multipliers
-
K'Andrea C. Bickersta, Michael J. Schulte, and Earl E. Swartzlander, Jr., "Reduced area multipliers, " Proc. International Conference on Application-Specic Array Processors, pp. 478-489, 1993.
-
(1993)
Proc International Conference on Application-Specic Array Processors
, pp. 478-489
-
-
Bickersta, K.C.1
Schulte, M.J.2
Earl, E.S.3
-
18
-
-
0026103250
-
An area model for on-chip memories and its application
-
Johannes M. Mulder, Nhon T. Quach, and Michael J. Flynn, "An area model for on-chip memories and its application, " IEEE Journal of Solid-State Circuits, vol. 26, pp. 98-106, 1991.
-
(1991)
IEEE Journal of Solid-State Circuits
, vol.26
, pp. 98-106
-
-
Mulder, J.M.1
Quach, N.T.2
Flynn, M.J.3
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