Enhanced FPGA reliability through efficient run-time fault reconfiguration

IEEE Transactions on Reliability

Volumn 49, Issue 3, 2000, Pages 296-304

  Lach, John ^a,b   Mangione Smith, William H ^a,c   Potkonjak, Miodrag ^a,c  

^a IEEE   (United States)

^b University of Virginia   (United States)

^c Engineering IV   (United States)

Author keywords

Fault tolerance; Field programmable gate array (FPGA); Online

Indexed keywords

RUN-TIME FAULT RECONFIGURATION;

ALGORITHMS; COMPUTER AIDED DESIGN; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; REAL TIME SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034260104     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/24.914546     Document Type: Article

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