High level synthesis techniques for efficient built-in-self-repair

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 1993-January, Issue , 1993, Pages 41-48

  Guerra, Lisa M ^a   Potkonjak, Miodrag M ^b   Rabaey, Jan M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; FAULT TOLERANCE; HEURISTIC ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUITS; REPAIR;

ALGORITHM DEVELOPMENT; ASIC DESIGN; BUILT IN SELF REPAIRS; FAULT TOLERANCE TECHNIQUES; HARDWARE REDUNDANCY; SCHEDULING TECHNIQUES; STATISTICAL METHODOLOGIES; YIELD IMPROVEMENT;

HIGH LEVEL SYNTHESIS;

EID: 0002058995     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1993.595623     Document Type: Conference Paper

References (0)