Solving the I/O bandwidth problem in system on a chip testing

Proceedings - 13th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2000, Pages 9-14

  Maroufi, W ^a   Benabdenbi, M ^a   Marzouki, M ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

Author keywords

Bandwidth; Content addressable storage; Degradation; Laboratories; Performance evaluation; Pins; Switches; System testing; System on a chip; Wires

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASSOCIATIVE STORAGE; BANDWIDTH; DEGRADATION; ECONOMIC AND SOCIAL EFFECTS; INTEGRATED CIRCUITS; LABORATORIES; SWITCHES; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; WIRE;

EXPANSION METHODS; PERFORMANCE EVALUATION; PINS; RECONFIGURABILITY; SYSTEM ON A CHIP; SYSTEM TESTING; SYSTEM-ON-A-CHIP TESTING; TEST ACCESS MECHANISM;

MICROPROCESSOR CHIPS;

EID: 67649940146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2000.876001     Document Type: Conference Paper

References (12)

1. E.J. Marinissen, Y. Zorian, R. Kapur, T.Taylor, and L. Whetsel. Towards a standard for embedded core test: An example. In IEEE International Test Conference (ITC), pages 616-627, Atlantic City, NJ, September 1999.
2. L. Whetsel. Addressable test ports an approach to testing embedded cores. In IEEE International Test Conference (ITC), pages 1055-1064, Atlantic City, NJ, September 1999.
3. E. J. Marinissen and al. A structured and scalable mechanism for test access to embedded reusable cores. In International Test Conference, Washington, DC, October 1998.
4. P. Varma and S. Bhatia. A structured test re-use methodology for core-based system chips. In International Test Conference, Washington, DC, October 1998.
5. D. Bhattacharya. Hierarchical test acces architecture for embedded cores in an integrated circuit. In IEEE VLSI Test Symposium (VTS), pages 8-14, Dana Point, CA, April 1998.
6. L. Whetsel. An ieee 1149.1 based test acces architecture for ics with embedded cores. In IEEE International Test Conference (ITC), pages 69-78, Washington, DC, November 1997.
7. W. Maroufi. A new compression/decompression method for non correlated test patterns: Application to test pins expansion. In IEEE European Test Workshop (ETW), Cascais, Portugal, May 2000.
8. A. Jas, J. Ghosh-Dastidar, and N. A. Touba. Scan vector compression/decompression using statistical coding. In 17th IEEE VLSI Test Symposium, San Diego, California, April 1999.
9. A. Jas and N A. Touba. Test vector decompression via cyclical scan chains and its application to testing core-based designs. In International test conference, pages 458-464, 1998.
10. M. Benabdenbi, W. Maroufi, and M. Marzouki. Cas-bus: A scalable and reconfigurable test acces mechanism for systems on a chip. In IEEE Design Automation and Test in Europe (DATE), pages 141-145, Paris, Prance, March 2000.
11. W. Maroufi, M. Benabdenbi, and M. Marzouki. Controlling the cas-bus tam with ieee 1149.1 tap: A solution for systems on a chip testing. In 4th IEEE International Workshop on Testing Embedded Core-Based System-Chips, Montreal, Quebec, Canada, May 2000.
12. J. van Beers and Harry van Herten. Test features of a core-based co-processor array for video applications. In International Test Conference, pages 638-647, Atlantic city, NJ, September 1999.