Testing for interconnect crosstalk defects using on-chip embedded processor cores

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 529-538

  Chen, Li ^a   Bai, Xiaoliang ^a   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Crosstalk; Interconnect; Processor; Self test

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER HARDWARE; COMPUTER SIMULATION; CROSSTALK; ERROR DETECTION; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT MANUFACTURE; RELIABILITY;

EMBEDDED PROCESSOR; INTERCONNECT CROSSTALK DEFECT; PROCESSOR-MEMORY SYSTEM; SYSTEM-ON-CHIP;

BUILT-IN SELF TEST;

EID: 0036693108     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016562011549     Document Type: Article

References (18)

1. High-level crosstalk defect simulation for system-on-chip interconnects
2. Self-test methodology for at-speed test of crosstalk in chip interconnects
3. Instruction randomization self test for processor cores
4. Software-based self-testing methodology for processor cores
5. Test generation in VLSI circuits for crosstalk noise
6. Test generation for crosstalk-induced delay in integrated circuits
7. Crosstalk minimization in three-layer HVH channel routing
8. Fault modeling and simulation for crosstalk in system-on-chip interconnects
9. An algorithmic test generation method for crosstalk faults in synchronous sequential circuits
10. Interconnect tuning strategies for high-performance ICs
11. Automatic test pattern generation for crosstalk glitches in digital circuits
12. Signal integrity problems in deep submicron arising from interconnects between cores
13. Arithmetic built-in self-test for DSP cores
14. Native mode functional test generation for processors with applications to self test and design validation
15. Validation and test generation for oscillatory noise in VLSI interconnects
16. Global routing with crosstalk constraints