Algorithmic test generation method for crosstalk faults in synchronous sequential circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 22-27

  Itazaki, Noriyoshi ^a   Matsumoto, Yasuyuki ^a   Kinoshita, Kozo ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC TEST GENERATION METHOD;

ALGORITHMS; COMPUTER SIMULATION; CROSSTALK; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0031362121     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. N. Itazaki, Y. Idomoto, and K. Kinoshita, "A fault simulation method for crosstalk faults in synchronous sequential circuits," IEICE Trans. on Info. and Syst., Vol. E80-D, No. 1, pp.38-43(Jan. 1997).
2. A. Rubio, N. Itazaki, X Xu and K. Kinoshita, "An approach to the analysis and detection of crosstalk faults in digital VLSI circuits," IEEE Trans. on CAD, Vol. 13, No. 3, pp. 387-395(Mar. 1994).
3. R. Anglada and A. Rubio, "An approach to crosstalk effect analysis and avoidance techniques in digital CMOS VLSI circuits," Int'l J. of Electronics, Vol. 6, No. 5, pp. 9-17(1988).
4. T. Kelsey and K. Saluja, "Fast test generation for sequential circuit," ICCAD-89, pp.345-357.
5. F. Brglez, D. Bryan and K. Kozminski, "Combinational profiles of sequential benchmark circuits," Proc. of Int'l Sympo. on Circuits and Systems, pp. 1929-1934(1989).