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Volumn 46, Issue 5, 1999, Pages 927-932

An asymmetric memory cell using a c-tft for single-bit-line sram's

Author keywords

(SNM); Asymmetric memory cell (amc); Cell ratio; Complementary tft (c tft); Low power; Low voltage; N channel tft; P channel tft; Single bit line; SRAM; Static noise margin

Indexed keywords

GATES (TRANSISTOR); THIN FILM TRANSISTORS;

EID: 0032664319     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.760399     Document Type: Article
Times cited : (8)

References (13)
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  • 2
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  • 3
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    • 16 Mbit SRAM Cell technologies for 2.0 V operation in IEDM Tech.
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  • 4
    • 85177000517 scopus 로고    scopus 로고
    • A large cell-ratio and low node leak 16 M-bit SRAM cell using ring-gate transistors in IEDM Tech.
    • K. Yuzuriha et al. A large cell-ratio and low node leak 16 M-bit SRAM cell using ring-gate transistors in IEDM Tech. Dig. abstr. 17.6 pp. 485-188 1991.
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    • Yuzuriha, K.1
  • 5
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    • A stacked split word-line (SSW) cell for low voltage operation large capacity high speed SRAM's in IEDM Tech.
    • S. Ikeda et al. A stacked split word-line (SSW) cell for low voltage operation large capacity high speed SRAM's in IEDM Tech. Dig. pp. 809-812 1993.
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  • 6
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  • 9
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    • A single-bit-line cross-point cell activation (SPCPA) architecture for ultra-low-power SRAM's IEEE J.
    • M. Ukita et al. A single-bit-line cross-point cell activation (SPCPA) architecture for ultra-low-power SRAM's IEEE J. Solid-State Circuits vol. SC-28 pp. 1114-1118 Nov. 1993.
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  • 12
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    • A high performance polysilicon TFT Using RTA and plasma hydrogenation applicable to highly stable SRAM of 16 Mbit and beyond in Symp.
    • F. Hayashi et al. A high performance polysilicon TFT Using RTA and plasma hydrogenation applicable to highly stable SRAM of 16 Mbit and beyond in Symp. VLSI Technology Dig. Tech. Papers June 1992 pp. 36-37.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.